The invention relates broadly to a test apparatus for random access memory (RAM) devices, and in particular to a fault tolerant test apparatus for large capacity random access memory units.
Accurate and economical fault testing of random access memory devices is a problem that has been addressed with great intensity by the computer industry. Fault tolerant testing of large random access memories is also the subject of intensive research both in the industry and in universities. The present test apparatus is the first of its kind that provides a unified solution to problems that have been tackled individually. One of the prior art techniques of defect tolerance during RAM testing has been implemented by integrating redundant rows and columns and using laser programming or other techniques to switch out faulty cells. References (2), (3), (6), (8) are some examples of the publications that propose this technique. Another technique proposed is the use of on Chip Error Correcting Codes. References (7) and (9) are examples of this approach. Design for testability has been proposed in references (10) and (1). The first modifies the sense amplifiers of the dynamic RAM to form a circular shift register of the RAM array. An on chip test pattern generator initializes this array which is then circulated and this action executes a test algorithm. The second basically implements the algorithm in references (4), (5) on chip.